CODIGO QUARTUS 1.6

 library ieee;

use ieee.std_logic_1164.all;

entity E_1_6 is 

port

  (A, B, C: in std_logic;

  L: out std_logic);

end E_1_6;

architecture db of E_1_6 is 

 signal S1: std_logic_vector (2 downto 0);

begin

  S1 <= A & B & C; 

with S1 select

  L <= '1' when "111",

  '0' when others;

end db;