PROGRAMACION VHDL E1.2 5 ENTRADAS

 CÓDIGO

library ieee;

use ieee.std_logic_1164.all;

entity E_1_2 is 

port

  (A, B, C, D, E: in std_logic;

  F: out std_logic);

end E_1_2;

architecture db of E_1_2 is 

 signal S1: std_logic_vector (4 downto 0);

begin

  S1 <= A & B & C & D & E; 

with S1 select

  F <= '0' when "00001" | "00011" | "00101" | "00111" | "01001" | "10001" | "11001",

  '1' when others;

end db