Investigación-Lógica Secuencial Síncrona FNVL. Ismael sampedro morales
Robot funcionando con switch FPGA
García García Antonio Alberto Montes Tlahuiz Armando Romero Pérez Juan Sampedro Morales Ismael Ortega Báez Marco Vital Felipe Neri
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Sumador completo FNVL
Felipe Neri Vital López
E1.4 - Código - quartus
CÓDIGO library ieee; use ieee.std_logic_1164.all; entity E_1_4 is port (A, B, C, D: in std_logic; F: out std_logic); end E_1_4; architecture db of E_1_4 is signal S1: std_logic_vector (3 downto 0); begin S1 <= A & B & C & D; with S1 select F <= '1' when "0001" | "0010" | "0011" | "1001" | "1010" | "1101" | "1110", '0' when others; end db;
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