Decodificador con display - FNVL
Felipe Neri Vital López
Entradas
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CODIGO QUARTUS 1.6
library ieee; use ieee.std_logic_1164.all; entity E_1_6 is port (A, B, C: in std_logic; L: out std_logic); end E_1_6; architecture db of E_1_6 is signal S1: std_logic_vector (2 downto 0); begin S1 <= A & B & C; with S1 select L <= '1' when "111", '0' when others; end db;
PROGRAMACION VHDL E1.2 5 ENTRADAS
CÓDIGO library ieee; use ieee.std_logic_1164.all; entity E_1_2 is port (A, B, C, D, E: in std_logic; F: out std_logic); end E_1_2; architecture db of E_1_2 is signal S1: std_logic_vector (4 downto 0); begin S1 <= A & B & C & D & E; with S1 select F <= '0' when "00001" | "00011" | "00101" | "00111" | "01001" | "10001" | "11001", '1' when others; end db
E1.5 CÓDIGO QUARTUS
CÓDIGO library ieee; use ieee.std_logic_1164.all; entity E_1_5 is port (A, B, C, D: in std_logic; G: out std_logic); end E_1_5; architecture db of E_1_5 is signal S1: std_logic_vector (3 downto 0); begin S1 <= A & B & C & D; with S1 select G <= '0' when "0000" | "1111", '1' when others; end db;
E1.3 Codigo - quartus
CÓDIGO library ieee; use ieee.std_logic_1164.all; entity E_1_3 is port (A, B, C: in std_logic; G: out std_logic); end E_1_3; architecture db of E_1_3 is signal S1: std_logic_vector (2 downto 0); begin S1 <= A & B & C; with S1 select G <= '1' when "011" | "110" | "111", '0' when others; end db;
E1.4 - Código - quartus
CÓDIGO library ieee; use ieee.std_logic_1164.all; entity E_1_4 is port (A, B, C, D: in std_logic; F: out std_logic); end E_1_4; architecture db of E_1_4 is signal S1: std_logic_vector (3 downto 0); begin S1
E1.1 CÓDIGO QUARTUS
E1.1 CÓDIGO library ieee; use ieee.std_logic_1164.all; entity E1_1 is port (A, B, C, D: in std_logic; F: out std_logic); end E1_1; architecture db of E1_1 is signal S1: std_logic_vector (3 downto 0); begin S1 <= A & B & C & D; with S1 select F <= '1' when "0000" | "0010" | "0011" | "0100" | "0110" | "0111" | "1010" | "1011", '0' when others; end db; CÓDIGO library ieee; use ieee.std_logic_1164.all; entity E_1_1_G is port (A, B, C, D: in std_logic; G: out std_logic); end E_1_1_G; architecture db of E_1_1_G is signal S1: std_logic_vector (3 downto 0); begin S1 <= A & B & C & D; with S1 select G <= '1' when "0000" | "0100" | "1000" | "1001" | "1010" | "1011" | "1100" | "1101", '0' when others; end db;
